The present invention relates generally to a semiconductor device, and more particularly, to an electrostatic discharge device that is capable of protecting a semiconductor device from static electricity and ensuring a pin capacitance using a metal option.
Generally, a semiconductor device has an electrostatic discharge device provided between an input/output pad and an internal circuit. The electrostatic discharge device performs an electrostatic discharge operation to protect the internal circuit of the semiconductor device from static electricity that is induced.
If the static electricity is induced within the semiconductor device, the static electricity concentrates and flows to the most vulnerable portion within the semiconductor device. As a result of the concentrated static electricity, failures such as junction, contact, or melting of the gate oxide may occur at the internal circuit of the semiconductor device. Therefore, the input/output pad of the semiconductor device is provided with the electrostatic discharge device to protect the internal circuit from the static electricity.
Currently, semiconductor chips are required to be capable of being operated at high speeds. Accordingly, a pin capacitance and its margin tend to be reduced, which results in increased difficulty in optimizing a pin capacitance characteristic.
Further, the semiconductor device is gradually being implemented in a smaller area. However, since semiconductor devices such as a Synchronous Dynamic (SD) RAM or a Double Date Rate (DDR) RAM requires a higher capacitance, it is difficult to implement the semiconductor devices in a smaller area while satisfying a demand for the higher capacitance.
General methods for addressing the above-mentioned problems include, a method of applying a gate oxide capacitor having a high capacitance relative to the area surrounding the pad formed in the semiconductor device for the electrostatic discharge device, or a method of modifying a package routing pattern of the semiconductor device to use a package capacitance of the semiconductor device for the electrostatic discharge device.
In particular, all of the devices used for the electrostatic discharge device such as a diode, a MOS transistor, or a Silicon Controlled Resistor (SCR), have a characteristic dependent upon the junction capacitance, and therefore have a capacitance which is considerably low.
Therefore, the electrostatic discharge device needs to be designed having sufficient capacitance while also being capable of being implemented in a smaller area.
FIG. 1 is a diagram showing an example of an electrostatic discharge circuit according to the prior art.
The electrostatic discharge circuit of the prior art shown in FIG. 1 includes an electrostatic discharging unit 10 for discharging the static electricity externally applied to a power source voltage Vcc line or a ground voltage Vss line, a protection unit 20 for protecting a gate oxide film of the input buffer 40, i.e., the internal circuit, from being destroyed due to charges stored in the discharging unit 10, a capacitor unit 30 for preventing excessive voltage from being applied to a gate to protect the oxide film from being destroyed, and an input buffer 40, i.e., the internal circuit, to which a signal is applied through a pad PAD.
The electrostatic discharging unit 10 includes a PMOS discharging diode 11 and an NMOS discharging diode 12 for discharging the static electricity induced at the pad PAD to a power source voltage Vcc line or a ground voltage Vss line, and a PMOS diode 13 and an NMOS diode 14 for adjusting a discharging capacity. The PMOS diode 13 and the NMOS diode 14 are connected to a node that is connected to the PAD by a metal option 15. The metal option 15 can be connected to the node connected to the pad PAD or cut to disconnect the node connected to the pad PAD to adjust the discharging capacity of the electrostatic discharging unit 10.
The protection unit 20 includes a resistance element R connected in series between the pad PAD and the input buffer 40, and an NMOS diode 21 connected to the resistance element R. The NMOS diode 21 is connected in parallel to the input buffer 40. The NMOS diode 21 is turned on to protect the gate oxide film from being destroyed if current due to the static electricity induced to the electrostatic discharging unit 10 abruptly flows.
The capacitor unit 30 includes a PMOS capacitor 31 connected to the power source Vcc line and an NMOS capacitor 32 connected to the ground voltage Vss line.
The MOS capacitors 31, 32 are connected to a rear portion of the resistor element R of the discharging unit 20, i.e., between the discharging unit 20 and the input buffer 40, and is responsible for diminishing excessive voltage applied to the input buffer 40 due to the static electricity. The MOS capacitors 31, 32 are responsible for protecting the gate oxide film of the input buffer 40 from being destroyed and also used for ensuring the pin capacitance. That is, where the specified pin capacitance cannot be ensured with diodes of the electrostatic discharging unit, the capacitor unit 30 is used for ensuring the pin capacitance.
However, there is a problem in that the overall chip size of the semiconductor device increases since all the pins of the semiconductor device must be formed with the capacitor to ensure the pin capacitance.